RESEARCH CONTEXT

As a consequence of the scaling of device dimensions to nanometer size, we face a multitude of challenges in designing complex giga-scale systems. Major challenges come from:

• Parametric Variation: intra- and inter-die variation of channel length, oxide thickness, doping concentration of MOS devices, which may cause large performance and power consumption degradations with respect to nominal circuits.
• Power Consumption: power dissipation is defined as the rate of energy delivered from the source to the system. Power dissipation is important for portable systems, as it defines the average lifetime of the battery. Moreover, higher power densities are the main source of on-chip temperature increase.
• Chip Temperature: Elevated temperatures are a major contributor to lower semiconductor reliability. If heat is not removed at a rate equal to or greater than its rate of generation, junction temperatures will rise. Higher junction temperatures reduce mean time to failure (MTTF) for the devices. Device reliability has a direct impact on the overall system reliability.
• Circuit Aging: due to high operating temperature, reliability of circuits is becoming a key issue. Due to thermally-induced physical effects, MOS devices (especially pMOS devices) are slowed-down. This implies a slow performance degradation of the entire circuit over time. In other words circuits become older and their maximum operating frequency reduces
  

In this scenario, variation-aware design is becoming a must in nowadays integrated circuits. All the big EDA and Silicon Vendors are integrating new optimization design techniques in their design flow. EDA group, in collaboration with several industrial partners (e.g., Synopsys, STMicroelectronics), is directing pioneer research on this fascinating area.  

AVAILABLE THESIS

Main purpose of the thesis is the design and integration of embedded monitors for run-time analysis of digital circuits. The variation monitors are in charge of estimating (run-time) the performance of the circuit, thus providing information about the actual deviation from nominal behaviour. The measured data can be used by dedicated on-chip control unit to compensate variation-induced performance degradation.

Background Knowledge: CMOS technologies and digital design at architectural and gate level.

Duration: 4-to-6 months full-time

Contact:

enrico[dot]macii[at]polito.it 

massimo[dot]poncino[at]polito.it

andrea[dot]calimera[at]polito.it